Silicon Design Engineer ( W2 ROLE )
12 Months Contract with possible extension
Boxborough MA (Onsite From Day 1)
The Role:
The candidate will be a member of the Memory I/O design team designing High Speed IO circuits and implementing DDR IPs. The focus of the activity will be centered around spice simulations and behavior modeling. The supporting team is an established group of talented Analog/Mixed-Signal integrated circuit designers. The site includes the direct supervisor, AMS manager, IP director, and majority of the AMS team.
Requirements:
• Circuit simulation with hspice/spectre
• Circuit behavioral modeling with systemVerilog including Real Number Modeling
• Data manipulation and analysis with TCL and Python
• Familiarity with transistor level circuit analysis
• Familiarity with Linux Command Line Interface
• Familiarity with Revision Control System (perforce preferred)
• Good documentation and communication skills
Responsibilities:
• Run spice simulations for circuits that include Transmitter, Receiver – CTLE/DFE, DLL, DAC, OpAmp, Comparator and voltage regulators.
• Write behavioral models of circuit characteristics in systemVerilog
• Work on tools and document best methods
• Participate and contribute to the definition of development flows that improve efficiency and quality of execution
Preferred Skilled Sets:
• A successful track record in circuit design for High Speed IOs
• Good knowledge of Design Verification flow
• Ability to dig into RTL or FW code supporting the custom circuit implementation.
• Ability to understand complex tool integrations and create and modify scripts to improve them .
Education Requirements
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